You will learn about the Clock and Resets of the FPGA and how to use themFPGAs/CPLDs are actual components that receiving real signals from the outside world. Some of them will be synchronized signals that has a clock. You will learn how to use the clocks and the resets to sample new data and create data/communication with the outside world.
The course contains over 50 lectures that will teach you the syntax of the VHDL code
In the end of the course we will complete together 6 ExercisesYou will learn how to code the VHDL by practice. Starting from the most basic VHDL code with Increasing task difficulty enhances I will show you in these videos how to write the code in the right way.
In the end of the course I will upload the last exercise code to a real FPGA! (with my Xilinx development board)I will also show you in real-time how I can debug the code with a real time debugger which is the Integrated logic analyzer of Xilinx.
This Course was made for all levels by a professional electronic and computer engineer. with a huge experience with FPGAs of all of the companies in the market.
Who this course is for:
- Anyone who wants to know VHDL and how to code in VHDL
- Anyone who wants to know FPGAs/CPLDs world
- Anyone who wants a better resume for his next job with a must knowledge for any Hitech company
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